The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures

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Title: The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
Authors: Thomas, DB
Luk, W
Item Type: Journal Article
Issue Date: 26-Apr-2012
URI: http://hdl.handle.net/10044/1/15310
DOI: http://dx.doi.org/10.1109/TVLSI.2012.2194171
ISSN: 1063-8210
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Start Page: 761
End Page: 770
Journal / Book Title: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 21
Issue: 4
Copyright Statement: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publication Status: Published
Appears in Collections:Computing
Electrical and Electronic Engineering



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