IRUS Total

Transparent In-Circuit Assertions for FPGAs

File Description SizeFormat 
tcad_journal.pdfAccepted version628.06 kBAdobe PDFView/Open
Title: Transparent In-Circuit Assertions for FPGAs
Authors: Hung, E
Todman, T
Luk, W
Item Type: Journal Article
Abstract: Commonly used in software design, assertions are statements placed into a design to ensure that its behaviour matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. We propose a new HDL-agnostic language for describing latency-insensitive assertions and novel methods to add such assertions transparently to an already placed-and-routed circuit without affecting the existing design. We also describe how this language and associated methods can be used to implement semi-transparent exception handling. The key to our work is that by treating hardware assertions and exceptions as being oblivious or less sensitive to latency, assertion logic need only use spare FPGA resources. We use network-flow techniques to route necessary signals to assertions via spare flip-flops, eliminating any performance degradation, even on large designs (92% of slices in one test). Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above 200MHz, at the cost of a small power penalty.
Issue Date: 20-Oct-2016
Date of Acceptance: 21-Sep-2016
URI: http://hdl.handle.net/10044/1/41804
DOI: https://dx.doi.org/10.1109/TCAD.2016.2618862
ISSN: 0278-0070
Publisher: IEEE
Start Page: 1193
End Page: 1202
Journal / Book Title: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume: 36
Issue: 7
Copyright Statement: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Commission of the European Communities
Engineering & Physical Science Research Council (E
Commission of the European Communities
Commission of the European Communities
Engineering & Physical Science Research Council (E
Funder's Grant Number: EP/I012036/1
PO 1553380
FP7 - 318521
516075101 (EP/N031768/1)
Keywords: Science & Technology
Computer Science, Hardware & Architecture
Computer Science, Interdisciplinary Applications
Engineering, Electrical & Electronic
Computer Science
Circuits and systems
design automation
electronic design automation and methodology
field programmable gate arrays
integrated circuits
logic design
reconfigurable logic
0906 Electrical And Electronic Engineering
1006 Computer Hardware
Computer Hardware & Architecture
Publication Status: Published
Appears in Collections:Faculty of Engineering
Electrical and Electronic Engineering