A nanosecond-level hybrid table design for financial market data generators

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Title: A nanosecond-level hybrid table design for financial market data generators
Authors: Fu, H
He, C
Luk, W
Li, W
Yang, G
Item Type: Conference Paper
Abstract: This paper proposes a hybrid sorted table design for minimizing electronic trading latency, with three main contributions. First, a hierarchical sorted table with two levels, a fast cache table in reconfigurable hardware storing megabytes of data items and a master table in software storing gigabytes of data items. Second, a full set of operations, including insertion, deletion, selection and sorting, for the hybrid table with latency in a few cycles. Third, an on- demand synchronization scheme between the cache table and the master table. An implementation has been developed that targets an FPGA-based network card in the environment of the China Financial Futures Exchange (CFFEX) which sustains 1- 10Gb/s bandwidth with latency of 400 to 700 nanoseconds, providing an 80- to 125-fold latency reduction compared to a fully optimized CPU-based solution, and a 2.2-fold reduction over an existing FPGA-based solution.
Issue Date: 30-Apr-2017
Date of Acceptance: 6-Mar-2017
URI: http://hdl.handle.net/10044/1/45622
Publisher: IEEE
Copyright Statement: This paper is embargoed until publication.
Sponsor/Funder: Engineering & Physical Science Research Council (E
Commission of the European Communities
Engineering & Physical Science Research Council (E
Engineering & Physical Science Research Council (EPSRC)
Funder's Grant Number: PO 1553380
516075101 (EP/N031768/1)
Conference Name: The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines
Publication Status: Accepted
Start Date: 2017-04-30
Finish Date: 2017-05-02
Conference Place: Napa, CA, USA
Embargo Date: publication subject to indefinite embargo
Appears in Collections:Faculty of Engineering