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F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks

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Title: F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks
Authors: Zhao, W
Fu, H
Luk, W
Yu, T
Wang, S
Feng, B
Ma, Y
Yang, G
Item Type: Conference Paper
Abstract: This paper presents a novel reconfigurable framework for training Convolutional Neural Networks (CNNs). The proposed framework is based on reconfiguring a streaming datapath at runtime to cover the training cycle for the various layers in a CNN. The streaming datapath can support various parameterized modules which can be customized to produce implementations with different trade-offs in performance and resource usage. The modules follow the same input and output data layout, simplifying configuration scheduling. For different layers, instances of the modules contain different computation kernels in parallel, which can be customized with different layer configurations and data precision. The associated models on performance, resource and bandwidth can be used in deriving parameters for the datapath to guide the analysis of design trade-offs to meet application requirements or platform constraints. They enable estimation of the implementation specifications given different layer configurations, to maximize performance under the constraints on bandwidth and hardware resources. Experimental results indicate that the proposed module design targeting Maxeler technology can achieve a performance of 62.06 GFLOPS for 32-bit floating-point arithmetic, outperforming existing accelerators. Further evaluation based on training LeNet-5 shows that the proposed framework achieves about 4 times faster than CPU implementation of Caffe and about 7.5 times more energy efficient than the GPU implementation of Caffe.
Issue Date: 1-Dec-2016
Date of Acceptance: 6-Jul-2016
URI: http://hdl.handle.net/10044/1/50990
DOI: https://dx.doi.org/10.1109/ASAP.2016.7760779
ISSN: 2160-052X
Publisher: IEEE
Start Page: 107
End Page: 114
Journal / Book Title: Application-specific Systems, Architectures and Processors (ASAP), 2016 IEEE 27th International Conference on
Copyright Statement: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (E
Commission of the European Communities
Engineering & Physical Science Research Council (E
Funder's Grant Number: PO 1553380
671653
516075101 (EP/N031768/1)
Conference Name: 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Keywords: Science & Technology
Technology
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Computer Science
Engineering
Publication Status: Published
Start Date: 2016-07-06
Finish Date: 2016-07-08
Conference Place: Imperial Coll London, London, ENGLAND
Appears in Collections:Faculty of Engineering
Computing