A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN

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Title: A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN
Authors: Aggleton, R
Ardila-Perez, L
Ball, FA
Balzer, MN
Brooke, J
Calligaris, L
Caselle, M
Cieri, D
Clement, EJ
Hall, G
Harder, K
Hobson, PR
Iles, GM
James, T
Manolopoulos, K
Matsushita, T
Morton, AD
Newbold, D
Paramesvaran, S
Pesaresi, M
Reid, ID
Rose, AW
Sander, O
Schuh, T
Shepherd-Themistocleous, C
Shtipliyski, A
Summers, SP
Tapper, A
Tomalin, I
Uchida, K
Vichoudis, P
Weber, M
Item Type: Conference Paper
Abstract: The Compact Muon Solenoid (CMS) experiment at CERN is scheduled for a major upgrade in the next decade in order to meet the demands of the new High Luminosity Large Hadron Collider. Amongst others, a new tracking system is under development including an outer tracker capable of rejecting low transverse momentum particles by looking at the coincidences of hits (stubs) in two closely spaced sensor layers in the same tracker module. Accepted stubs are transmitted off-detector for further processing at 40 MHz. In order to maintain under the increased luminosity the Level-1 trigger rate at 750 kHz, tracker data need to be included in the decision making process. For this purpose, a system architecture has to be developed that will be able to identify particles with transverse momentum above 3 GeV/c by building tracks out of stubs, while achieving an overall processing latency of maximum 4us. Targeting these requirements the current paper presents an FPGA-based track finding architecture that identifies track candidates in real-time and bases its functionality on a fully time-multiplexed approach. As a proof of concept, a hardware system has been assembled targeting the MP7 MicroTCA processing card that features a Xilinx Virtex-7 FPGA, demonstrating a realistic slice of the track finder. The paper discusses the algorithms' implementation and the efficient utilisation of the available FPGA resources, it outlines the system architecture, and presents some of the hardware demonstrator results.
Issue Date: 2-Oct-2017
Date of Acceptance: 1-Sep-2017
URI: http://hdl.handle.net/10044/1/55089
DOI: https://dx.doi.org/10.23919/FPL.2017.8056825
ISBN: 9789090304281
Publisher: IEEE
Journal / Book Title: 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
Copyright Statement: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Conference Name: 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
Publication Status: Published
Start Date: 2017-09-04
Finish Date: 2017-09-08
Conference Place: Ghent, Belgium
Open Access location: http://ieeexplore.ieee.org/document/8056825/?reload=true
Appears in Collections:Physics
High Energy Physics



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