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Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis

Title: Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis
Authors: Yan, J
Yuan, J
Leong, PHW
Luk, W
Wang, L
Item Type: Journal Article
Abstract: As the density of field-programmable gate arrays continues to increase, the size of configuration bitstreams grows accordingly. Compression techniques can reduce memory size and save external memory bandwidth. To accelerate the configuration process and reduce the software startup time, four open-source lossless compression decoders developed using high-level synthesis techniques are presented. Moreover, in order to balance the objectives of compression ratio, decompression throughput, and hardware resource overhead, various improvements and optimizations are proposed. Full bitstreams and software binaries have been collected as a benchmark, and 33 partial bitstreams have also been developed and integrated into the benchmark. Evaluations of the synthesizable compression decoders are demonstrated on a Xilinx ZC706 board, showing higher decompression throughput than those of the existing lossless compression decoders using our benchmark. The proposed decoders can reduce software startup time by up to 31.23% in embedded systems and 69.83% reduction of reconfiguration time for partial reconfigurable systems.
Issue Date: 22-Jun-2017
Date of Acceptance: 26-May-2017
URI: http://hdl.handle.net/10044/1/56369
DOI: https://dx.doi.org/10.1109/TVLSI.2017.2713527
ISSN: 1063-8210
Publisher: Institute of Electrical and Electronics Engineers
Start Page: 2842
End Page: 2855
Journal / Book Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume: 25
Issue: 10
Copyright Statement: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Commission of the European Communities
Engineering & Physical Science Research Council (E
Funder's Grant Number: EP/I012036/1
516075101 (EP/N031768/1)
Keywords: Science & Technology
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Computer Science
Compression decoder
field programmable gate array (FPGA) bitstream
high-level synthesis (HLS)
lossless compression
software binary
0805 Distributed Computing
0906 Electrical And Electronic Engineering
1006 Computer Hardware
Computer Hardware & Architecture
Publication Status: Published
Appears in Collections:Faculty of Engineering