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Exploring the potential of reconfigurable platforms for order book update

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Title: Exploring the potential of reconfigurable platforms for order book update
Authors: He, C
Fu, H
Luk, W
Li, W
Yang, G
Item Type: Conference Paper
Abstract: The order book update (OBU) algorithm is widely used in financial exchanges for rebuilding order books. The number of messages produced has drastically increased over time. The software solutions become more and more difficult to scale with the growing message rate and meet the requirement of low latency. This paper explores the potential of reconfigurable platforms in revolutionizing the order book architecture, and proposes a novel order book update algorithm optimized for maximal throughput and minimal latency. Our approach has three main contributions. First, we derive a fixed tick data structure for the order book that is easier to be mapped to the hardware. Second, we design a customized cache storing the top five levels of the order book to further reduce the latency. Third, we propose a hardware-friendly order book update algorithm based on the data structures we proposed. In the experiment, our FPGA-based solution can process 1.2-1.5 million messages per second with the throughput of 10Gb/s and the latency of 132-288 nanoseconds, which is 90-157 times faster than a CPU-based solution, and 5.2-6.6 times faster than an existing FPGA-based solution.
Issue Date: 5-Oct-2017
Date of Acceptance: 4-Sep-2017
URI: http://hdl.handle.net/10044/1/56418
DOI: https://dx.doi.org/10.23919/FPL.2017.8056862
ISBN: 9789090304281
ISSN: 1946-1488
Publisher: IEEE
Journal / Book Title: Field Programmable Logic and Applications (FPL), 2017 27th International Conference on
Copyright Statement: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Sponsor/Funder: Engineering & Physical Science Research Council (EPSRC)
Engineering & Physical Science Research Council (E
Commission of the European Communities
Engineering & Physical Science Research Council (E
Funder's Grant Number: EP/I012036/1
PO 1553380
516075101 (EP/N031768/1)
Conference Name: Field Programmable Logic and Applications (FPL), 2017
Publication Status: Published
Start Date: 2017-09-04
Finish Date: 2017-09-08
Conference Place: Ghent, Belgium
Appears in Collections:Faculty of Engineering