Memory mapping for multi-die FPGAs

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Title: Memory mapping for multi-die FPGAs
Authors: Voss, N
Quintana, P
Mencer, O
Luk, W
Gaydadjiev, G
Item Type: Conference Paper
Abstract: This paper proposes an algorithm for mappinglogical to physical memory resources on Field-ProgrammableGate Arrays (FPGAs). Our greedy strategy based algorithmis specifically designed to facilitate timing closure on modernmulti-die FPGAs for static-dataflow accelerators utilising mostof the on-chip resources. The main objective of the proposedalgorithm is to ensure that specific sub-parts of the design underconsideration can fully reside within a single die to limit inter-die communication. The above is achieved by performing thememory mapping for each sub-part of the design separately whilekeeping allocation of the available physical resources balanced.As a result the number of inter-die connections is reduced onaverage by 50% compared to an algorithm targeting minimalarea usage for real, complex applications using most of the on-chip’s resources. Additionally, our algorithm is the only one outof the four evaluated approaches which successfully producesplace and route results for all 33 applications and benchmarks.
Issue Date: 28-Apr-2019
Date of Acceptance: 3-Mar-2019
URI: http://hdl.handle.net/10044/1/69950
Publisher: IEEE
Copyright Statement: This paper is embargoed until publication.
Conference Name: The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines
Publication Status: Accepted
Start Date: 2019-04-28
Finish Date: 2019-05-01
Conference Place: San Diego
Embargo Date: publication subject to indefinite embargo
Appears in Collections:Computing



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